1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit suitably applicable to analog multipliers.
2. Related Background Art
Among analog signal processes, highly accurate analog multiplication technology has been developed by many researchers. Particularly, the four-quadrant multiplier presented in the paper of "B. Gilbert, "A precision four-quadrant multiplier with subnanosecond response," IEEE J. Solid-State Circuits vol. SC-3, pp 365-373, December 1963" comes so far as the original model of multipliers of semiconductor integrated circuits, called Gilbert's multiplier. Since then, many analog multipliers have been suggested and developed, including "J. N. Babanezhad and G. C. Temes, "A 20-V four-quadrant CMOS analog multiplier,"IEEE J. Solid-State Circuits, vol. SC-20, pp 1158-1168, December 1985," "H. J. Song and C. K. Kim, "An MOS four-quadrant analog multiplier using simple two-input squaring circuits with source followers,"IEEE J. Solid-State Circuit, vol. 25, pp 841-847, June 1990," and so on. These circuits are characterized by use of bipolar transistors or MOS transistors. Among them, operating points of the MOS transistors were based on the operation in the mode where an inversion layer was formed in the channel with application of a voltage not less than Vth, i.e., the operation in the triode region and the saturation region of MOS transistor.
The core of operation of present signal processing utilizes many product-sum operations as in digital signal processing. When these processes were attempted to be replaced by parallel analog processes, many multipliers were necessitated and it was difficult in terms of electric power consumption to realize a circuit configuration composed of the MOS transistors that operate in the above-stated triode region and saturation region. A circuit, overcoming this problem, is a multiplier using the operation in the subthreshold region of MOS transistor as described in "A. G. Andreou, K. A. Boahen, P. O. Pouliquen, A. Pavasovic, R. E. Jenkins and K. Strohben, "Current-mode subthreshold MOS circuit for analog VLSI neural systems," IEEE Trans. Neural Networks, vol. 2, no 2, pp 205-pp 213" or "C. A. Mead, Analog VLSI and Neural Systems, Reading, MA: Addison-Wesley, 1989." FIG. 1 illustrates an example of a circuit diagram of a multiplier using the MOS transistors in the subthreshold region. The operation region of the MOS transistors in FIG. 1 is a weak inversion layer state where the gate-source voltage Vgs is far lower than the threshold voltage Vth and where a complete inversion layer is not formed in the channel, which is the subthreshold region in which the drain current Id is determined exponentially against values of the gate-source voltage Vgs. In FIG. 1, numeral 1 designates a first input current signal source having a value of Ix and 2 a second input signal source having a value of Iy. One terminal of the first signal current source 1 is connected to power-supply voltage 4 and a current output terminal being the other terminal thereof is connected to a common connection point A between a drain terminal of MOS transistor 52 and a gate terminal of MOS transistor 53 to supply a drain current Id52 of the MOS transistor 52. A source terminal of the MOS transistor 52 is connected to the ground potential 5 and a gate terminal thereof is connected to a source terminal of the MOS transistor 53 and to a drain terminal of MOS transistor 51. The source of the MOS transistor 51 is connected to the ground potential 5 and the gate terminal thereof is connected to a common connection point between the drain and the gate of MOS transistor 50 and to a current output terminal of the second input signal current source 2. The other terminal of the second input signal current source 2 is connected to the power-supply voltage 4. The MOS, transistor 50 and MOS transistor 51 compose a current mirror circuit to mirror an input of the current of the second input signal current source 2 and output the drain current Id51 of the MOS transistor 51. A third input signal current source 58 has the value of Iz, one terminal of the third input signal current source 58 being connected to the power-supply voltage 4 and the other terminal thereof supplying a current output to be injected to a common connection point between the gate and source terminals of MOS transistor 57 and the gate terminal of MOS transistor 56. The MOS transistor 57 and MOS transistor 56 compose a current mirror circuit to mirror Iz of the third input signal current source 58 and output the drain current Id56 of the MOS transistor 56. The drain terminal of the MOS transistor 56 is connected to a common connection point between the source terminal of MOS transistor 54 and the gate terminal of MOS transistor 55. The gate terminal of the MOS transistor 54 is connected to a common connection point A among the gate terminal of MOS transistor 53, the drain terminal of MOS transistor 52, and the current output terminal of the first input signal current source 1. The source terminal of MOS transistor 55 is connected to the ground potential 5 and an output current is taken out of the drain terminal thereof. Since the all MOS transistors operate in the subthreshold region, the drain current Id is determined exponentially against the gate-source voltage Vgs. Namely, the following relation holds: Id =I0.multidot.exp(Vgs/V0) or Vgs =V0.multidot.ln(Id/I0) (where I0, V0 are constants determined from device characteristics). The gate-source voltages of the MOS transistors 52, 50 receiving the first and second input signal currents Ix, Iy are given as follows: Vgs52=V0.multidot.ln(Ix/I0), Vgs50 32 V0.multidot.ln(Iy/I0). Since the MOS transistor 50 and MOS transistor 51 compose the current mirror, the drain current Id51 of the MOS transistor 51 is equal to Iy and thus the following relation holds: Id51=Iy. The drain current of the MOS transistor 53 is also equal to it, and thus the following relation holds: Iy=Id51=Id53. Therefore, the gate-source voltage of the MOS transistor 53 is given by Vgs53=V0.multidot.ln(Iy/I0).
The potential Va at the common connection point A is given as follows: Va=Vgs52+Vgs53=V0.multidot.ln(Ix/I0) +V0.multidot.ln(Iy/I0), which is an addition of logarithmic functions, and the potential Va=V0.multidot.ln(Ix.multidot.Iy/I0.sup.2) finally, thus obtaining the term of the product of input signals Ix, Iy. Since the third input signal current Iz is equal to the drain current Id56 of the MOS transistor 56 because of the current mirror circuit, the gate-source voltage Vgs54 of the MOS transistor 54 becomes Vgs54=V0.multidot.ln(Iz/I0). When the drain current of the MOS transistor 55 as an output current is Iout, Vgs55=V0.multidot.ln(Iout/I0). Therefore, the potential Va at the common connection point A is given as follows: Va=Vgs54+Vgs55 V0.multidot.ln(Iz/I0)+V0.multidot.ln(Iout/I0)=V0.multidot.ln(Iz-Iout/I0.su p.2), which is the form of the product of Iz and Iout. Namely, the following relation holds: Va=V0.multidot.ln(Ix=19 Iy/I0.sup.2)=V0.multidot.ln(Iz.multidot.Iout/I0.sup.2). Accordingly, the relation among the four currents is given by Ix.multidot.Iy=Iz-Iout. Therefore, the output current taken out of the drain terminal of the MOS transistor 55 at last is Iout=(Ix.multidot.Iy)/Iz, which is a current obtained by dividing the product of the input signal currents Ix, Iy by the input signal current Iz. Assuming Iz is a unit current 1, Iout =Ix.multidot.Iy, so that the product of the two input-signal currents emerges as an output current.
For realizing the above-stated circuit, however, there were some points to be improved. When attention is focused on the first and second input signal currents Ix, Iy in the first voltage adder composed of the MOS transistor 52 and MOS transistor 53 to create the potential Va=V0.multidot.ln(Ix.multidot.Iy/I0.sup.2) at the common connection point, the circuit is configured in such a form that the current Ix flows into the circuit while the current Iy flows out of the circuit. In this configuration, the direction of original input signal current Iy is turned by the current mirror composed of the MOS transistor 50 and MOS transistor 51 and the mirrored current Id51=Iy is pulled through the source terminal of the MOS transistor 53. This causes an error due to the current mirror of one stage to be superimposed on Iy and the current Iy with the error is applied to the first voltage adder. This drops the accuracy of Iy input. Since the drain voltage of the MOS transistor 52 for delivering Iy is clamped at the value of Vgs52 of the MOS transistor 52, the drain-source voltage Vds51 of the MOS transistor 51 is controlled to a very low voltage.
[Vds51=Vgs52=V0.multidot.ln(Ix/I0)]
Namely, the current value Iy set by the current mirror is not allowed to flow because of the low drain voltage, and thus Id51 becomes smaller than Iy. This sometimes degraded the accuracy of analog multiplication considerably. In addition, the circuit of FIG. 1 required the additional circuit for letting the unit current Iz flow, which increased the circuit scale.